1. Field of Invention
The present invention relates to a method for planarizing dynamic random access memory (DRAM). More particularly, the present invention relates to a method for planarizing DRAM cells.
2. Description of Related Art
In the manufacture of sub-micron very large scale integrated (VLSI) circuits or ultra large scale integrated (ULSI) circuits, planarization is a very important process. DRAM is a very common and widely used memory. FIGS. 1A through 1C are cross-sectional views showing the progression of manufacturing steps in the planarization of a DRAM cell by a conventional method. First, as shown in FIG. 1A, a silicon substrate 10 having a memory cell circuit region formed thereon is provided. The memory cell circuit region includes a field oxide layer 11, an oxide layer 12 and a capacitor 13.
Next, as shown in FIG. 1B, an insulating layer 14 is deposited over the silicon substrate and the memory cell circuit region.
In a conventional method for forming DRAM cells, since the capacitor 13 is formed above the memory cell circuit region, there will be a height difference between the top of the capacitor 13 and the surrounding memory cell circuit region. In the planarization of sub-half-micron integrated circuits, if the step height hc (shown in FIG. 1A) of a capacitor 13 is bigger than or equal to about 0.5 .mu.m, planarization becomes difficult, and may lead to poor structural quality in subsequent processes.
Next, for example, as shown in FIG. 1C, a subsequent metallization process is performed. In the metallization process, a photoresist layer is formed over the insulating layer 14, then light is shone onto the photoresist layer through a photomask having a desired pattern for forming conducting wires 15 and 16. Since the photoresist layer will react chemically when exposed to light, after development with chemicals, the desired etching pattern is formed. However, as mentioned before, because the difference in height between the top of the capacitor and its surrounding areas is big, there will be insufficient depth of focus during light exposure which may lead to defocusing. Therefore, pattern on the photoresist layer will be properly transferred and may ultimately lead to the deformation of conducting wires after the metallic etching operation. As a result, the resistance of a conductive wire such as 15 becomes larger.
To solve the problems caused by a difference in height levels, a chemical-mechanical polishing operation is generally applied. The chemical-mechanical polishing method is a global planarization method. Principly, the chemical-mechanical polishing method combines mechanical polishing with suitable chemical reagents, a slurry which is a mixture of colloidal silica and potassium hydroxide (KOH), and operates under a suitably controlled set of parameters to obtain an optimal planarity. The set of controlling parameters includes: slurry composition, magnitude of pressure on the wafer, rotational speed of the polishing head, material of the polishing pad, size distribution of polishing particles, working temperature, pH and so on. In general, all these parameters need to be changed according to the kind of material to be polished. Hence, chemical-mechanical polishing is a hard to control, costly and time consuming global planarization process. In light of the foregoing, there is a need in the art to improve the planarization method.